The present invention relates generally to computers and more specifically to systems and methods for enhancing observability of circuit designs described using behavioral level HDLs.
Digital circuit design is a complicated process. Initially, designers could design integrated circuits at the gate level. In other words, the designers would determine the particular arrangement and interconnection of logic gates (e.g., NAND or NOR gates) which would achieve the desired functionality. The physical layout of the logic gates could then be determined and the corresponding physical device constructed.
As the size and complexity of integrated circuits has increased, various automation tools have been developed to assist designers in their work. For example, physical layout EDA (Electronic Design Automation) tools can accept a structural gate level description and generate a physical configuration for the circuit. This provided designers with a level of abstraction which simplified the design process. This was the prevalent starting point for the design process until further increases in complexity required a higher level of abstraction.
Currently, typical circuit design methodology involves providing an abstracted description of the circuit and transforming it into a structural description with an aid of a synthesis tool. In other words, behavioral descriptions of various sub-components within the circuit are generated and then transformed by the synthesis tool into structural, gate level descriptions of the sub-components and the circuit.
At the behavioral level, a circuit (or sub-component of a circuit) can be described in terms of the inputs to the circuit, the outputs from the circuit, and the processes which are performed by the circuit and thereby transform the input signals into the output signals. The behavioral characterization of the circuit is normally provided in an HDL module or entity. HDL is an acronym for Hardware Description Language. HDLs are specifically designed to provide a means for specifying the behavior of a digital system or design at various levels of abstraction. (The terms xe2x80x9cdesignxe2x80x9d and xe2x80x9cdigital systemxe2x80x9d are used interchangeably throughout this description.) HDLs have evolved into two standards: Verilog and VHDL.
An HDL behavioral description is an abstraction of how a digital system works. This description is essentially a xe2x80x9cblack boxxe2x80x9d with a certain set of inputs and a certain set of outputs. The manner in which the outputs are generated from the inputs is described functionally, but not in terms of the specific arrangement of logic gates.
The HDL behavioral description is transformed into a gate-level structural description of the circuit by a synthesis tool. The synthesis tool reads the HDL behavioral description and generates a corresponding description which consists of a list of logic gates and the interconnections between the gates.
The synthesis tool is configured to optimize the generated design. In other words, if a particular set of functions can be performed either by a single gate component or a series of interconnected components, the synthesis tool will normally selected the single component, which would typically be configured to perform the function in a faster and more efficient manner.
While this optimization is typically desirable, there are situations in which it would be preferable to prevent full or partial optimization of the functional design. For instance, in order to easily debug the design, it may be helpful to have access to certain signals which are internal to the circuit. Thus, rather than simply being able to observe the inputs to the circuit and outputs from circuit, a designer could observe intermediate signals which allow him or her to isolate errors within particular portions of the circuit.
One or more of the problems outlined above may be solved by the various embodiments of the invention. Broadly speaking, the invention comprises systems and methods for enhancing the observability of circuit designs which are described using behavioral level HDLs. The systems and methods may, for example, provide means for correlating HDL behavioral description signal names to signals in the structural gate level description of the design.
In one embodiment, an HDL behavioral description of a circuit is processed by a correlation compiler to identify intermediate signals. The behavioral description is modified to specify that the intermediate signals are primary outputs of the circuit. The modified behavioral description is then processed by a synthesis tool to generate a structural description corresponding to the modified behavioral description. The structural description includes as outputs the identified intermediate signals.
In another embodiment, an HDL behavioral description of a design is provided in the same manner as in the first embodiment. In this instance, however, the HDL behavioral description is not modified by the correlation compiler. Instead, the correlation compiler generates a set of constraints that are formatted for use by the synthesis tool. These constraints, along with the original HDL behavioral description, forming a constrained HDL behavioral description which the synthesis tool transforms into a structural, gate level description.
In another embodiment, an HDL behavioral description is provided to a non-optimizing synthesis tool, rather than to a separate correlation compiler. The non-optimizing synthesis tool incorporates the functions of the correlation compiler described in the previous embodiments, but does not necessarily generate a modified behavioral description. The non-optimizing synthesis tool may instead provide various internal data structures and functions for identifying intermediate signals that are to be maintained in the structural description of the circuit.
In yet another embodiment, the initial HDL behavioral description is processed by a correlation compiler to generate a modified HDL behavioral description. The HDL behavioral description is modified in this embodiment by encapsulating each process which is contained in the description. That is, each process is identified and an independent HDL behavioral description corresponding to that process is generated. The individual HDL behavioral descriptions are then fed to the synthesis tool for processing. The synthesis tool generates a structural description for each of the individual HDL behavioral descriptions. These structural descriptions are then integrated to produce a structural description of the entire design. Depending upon the particular embodiment, the individual structural descriptions may be integrated into a single structural descriptions for the entire circuit by either the synthesis tool or the correlation compiler.